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Cost-efficient soft error protection for embedded microprocessors
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An Area-Efficient Approach to Improving Register File Reliability against Transient Errors
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Using Register Lifetime Predictions to Protect Register Files against Soft Errors
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Compiler-managed register file protection for energy-efficient soft error reduction
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A compiler optimization to reduce soft errors in register files
Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Static analysis to mitigate soft errors in register files
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Journal of Electronic Testing: Theory and Applications
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For embedded systems, where neither energy nor reliability can be easily sacrificed, this paper presents an energy efficient soft error protection scheme for register files (RFs). Unlike previous approaches, the proposed method explicitly optimizes for energy efficiency and can exploit the fundamental tradeoff between reliability and energy. While even simple compiler-managed RF protection scheme can be more energy efficient than hardware schemes, this paper formulates and solves further compiler optimization problems to significantly enhance the energy efficiency of RF protection schemes by an additional 30 % on average, as demonstrated in our experiments on a number of embedded application benchmarks.