A compiler optimization to reduce soft errors in register files
Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
A compiler-microarchitecture hybrid approach to soft error reduction for register files
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Software-based register file vulnerability reduction for embedded processors
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on ESTIMedia'10
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This paper studies approaches to exploiting the space both within or across registers efficiently for improving the register file reliability against transient errors. The idea of our approach is based on the fact that a large number of register values are narrow (i.e., less than or equal to 16 bits for a 32-bit architecture); therefore, the upper 16 bits of the registers can be used to replicate the short operands for enhancing register integrity. This paper also adapts a prior register replication approach by selectively copying register values (i.e., long operands only) to the unused physical registers for enhancing reliability without incurring significant hardware cost. Our experiments indicate that on average, 99.3% register reads (regardless of short or long operands) can find their replicas available, implying significant improvement of register file integrity against transient errors.