Resource-Driven optimizations for transient-fault detecting superscalar microarchitectures

  • Authors:

  • Jie S. Hu;G. M. Link;Johnsy K. John;Shuai Wang;Sotirios G. Ziavras

  • Affiliations:

  • Electrical and Computer Engineering, New Jersey Institute of Technology, Newark, NJ;Microsystems Design Lab, The Pennsylvania State University, University Park, PA;Electrical and Computer Engineering, New Jersey Institute of Technology, Newark, NJ;Electrical and Computer Engineering, New Jersey Institute of Technology, Newark, NJ;Electrical and Computer Engineering, New Jersey Institute of Technology, Newark, NJ

  • Venue:
  • ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
  • Year:
  • 2005

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Abstract

Increasing microprocessor vulnerability to soft errors induced by neutron and alpha particle strikes prevents aggressive scaling and integration of transistors in future technologies if left unaddressed. Previously proposed instruction-level redundant execution, as a means of detecting errors, suffers from a severe performance loss due to the resource shortage caused by the large number of redundant instructions injected into the superscalar core. In this paper, we propose to apply three architectural enhancements, namely 1) floating-point unit sharing (FUS), 2) prioritizing primary instructions (PRI), and 3) early retiring of redundant instructions (ERT), that enable transient-fault detecting redundant execution in superscalar microarchitectures with a much smaller performance penalty, while maintaining the original full coverage of soft errors. In addition, our enhancements are compatible with many other proposed techniques, allowing for further performance improvement.