Exploiting inactive rename slots for detecting soft errors

Authors:
Mehmet Kayaalp;Oğuz Ergin;Osman S. Ünsal;Mateo Valero
Affiliations:
Department of Computer Engineering, TOBB University of Economics and Technology, Ankara, Turkey;Department of Computer Engineering, TOBB University of Economics and Technology, Ankara, Turkey;Barcelona Supercomputing Center (BSC);Universitat Politecnica de Catalunya (UPC)
Venue:
ARCS'10 Proceedings of the 23rd international conference on Architecture of Computing Systems
Year:
2010

Citing 13
Cited 0

Trace cache: a low latency approach to high bandwidth instruction fetching

Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
Transient fault detection via simultaneous multithreading

Proceedings of the 27th annual international symposium on Computer architecture
Efficient dynamic scheduling through tag elimination

ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Transient-fault recovery using simultaneous multithreading

ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Detailed design and evaluation of redundant multithreading alternatives

ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
The Alpha 21264 Microprocessor

IEEE Micro
The Design Space of Register Renaming Techniques

IEEE Micro
A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor

Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Soft Errors in Advanced Computer Systems

IEEE Design & Test
Reducing Rename Logic Complexity for High-Speed and Low-Power Front-End Architectures

IEEE Transactions on Computers
Exploiting Narrow Values for Soft Error Tolerance

IEEE Computer Architecture Letters
Using Tag-Match Comparators for Detecting Soft Errors

IEEE Computer Architecture Letters
Resource-Driven optimizations for transient-fault detecting superscalar microarchitectures

ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture

Quantified Score

Hi-index	0.00

Visualization

Abstract

Register renaming is a widely used technique to remove false data dependencies in superscalar datapaths. Rename logic consists of a table that holds a physical register mapping for each architectural register and a logic for checking intra-group dependencies. This logic checking consists of a number of comparators that compares the values of destination and source registers. Previous research has shown that the full capacity of the dependency checking logic is not used at each cycle. In this paper we propose some techniques that make use of the unused capacity of the dependency checking logic of the rename stage in order to detect soft errors that occur on the register tags while the instructions are passing through the frontend of the processor.