Detailed design and evaluation of redundant multithreading alternatives

  • Authors:

  • Shubhendu S. Mukherjee;Michael Kontz;Steven K. Reinhardt

  • Affiliations:

  • Intel Corporation, Shrewsbury, MA;Hewlett-Packard Company, Fort Collins, CO;University of Michigan, Ann Arbor, Ann Arbor, MI

  • Venue:
  • ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
  • Year:
  • 2002

Quantified Score

Hi-index 0.00

Visualization

Abstract

Exponential growth in the number of on-chip transistors, coupled with reductions in voltage levels, makes each generation of microprocessors increasingly vulnerable to transient faults. In a multithreaded environment, we can detect these faults by running two copies of the same program as separate threads, feeding them identical inputs, and comparing their outputs, a technique we call Redundant Multithreading (RMT).This paper studies RMT techniques in the context of both single- and dual-processor simultaneous multithreaded (SMT) single-chip devices. Using a detailed, commercial-grade, SMT processor design we uncover subtle RMT implementation complexities, and find that RMT can be a more significant burden for single-processor devices than prior studies indicate. However, a novel application of RMT techniques in a dual-processor device, which we term chip-level redundant threading (CRT), shows higher performance than lockstepping the two cores, especially on multithreaded workloads.