Slipstream processors: improving both performance and fault tolerance

  • Authors:

  • Karthik Sundaramoorthy;Zach Purser;Eric Rotenburg

  • Affiliations:

  • North Carolina State University, Department of Electrical and Computer Engineering, Engineering Graduate Research Center, Campus Box 7914, Raleigh, NC;North Carolina State University, Department of Electrical and Computer Engineering, Engineering Graduate Research Center, Campus Box 7914, Raleigh, NC;North Carolina State University, Department of Electrical and Computer Engineering, Engineering Graduate Research Center, Campus Box 7914, Raleigh, NC

  • Venue:
  • ASPLOS IX Proceedings of the ninth international conference on Architectural support for programming languages and operating systems
  • Year:
  • 2000

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Abstract

Processors execute the full dynamic instruction stream to arrive at the final output of a program, yet there exist shorter instruction streams that produce the same overall effect. We propose creating a shorter but otherwise equivalent version of the original program by removing ineffectual computation and computation related to highly-predictable control flow. The shortened program is run concurrently with the full program on a chip multiprocessor simultaneous multithreaded processor, with two key advantages:1) Improved single-program performance. The shorter program speculatively runs ahead of the full program and supplies the full program with control and data flow outcomes. The full program executes efficiently due to the communicated outcomes, at the same time validating the speculative, shorter program. The two programs combined run faster than the original program alone. Detailed simulations of an example implementation show an average improvement of 7% for the SPEC95 integer benchmarks.2) Fault tolerance. The shorter program is a subset of the full program and this partial-redundancy is transparently leveraged for detecting and recovering from transient hardware faults.