Better exploration of region-level value locality with integrated computation reuse and value prediction

  • Authors:

  • Youfeng Wu;Dong-Yuan Chen;Jesse Fang

  • Affiliations:

  • Microprocessor Research Labs (MRL), Intel Corporation, Santa Clara, CA;Microprocessor Research Labs (MRL), Intel Corporation, Santa Clara, CA;Microprocessor Research Labs (MRL), Intel Corporation, Santa Clara, CA

  • Venue:
  • ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
  • Year:
  • 2001

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Abstract

Computation-reuse and value-prediction are two recent techniques for improving microprocessor performance by exploiting value localities. They both aim at breaking the data dependence limit in traditional processors. In this paper, we propose a speculative multithreading scheme in which the same hardware can be efficiently used for both computation reuse and value prediction. For the SpecInt95 benchmarks, our experiment shows that the integrated approach significantly out-performs either computation reuse or value prediction alone. For example, the integrated approach improves over computation reuse from a speedup of 1.25 to 1.40, and improves over value prediction from 1.28 to 1.40. In particular, the integrated approach out-performs a computation reuse configuration that has twice as much reuse buffer entries (from a speedup 1.33 to 1.40). Furthermore, unlike the computation reuse approach, the performance of the integrated approach does not rely on value profile during region formation and thus our approach is more suitable for production systems.