Exceeding the dataflow limit via value prediction
Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
The predictability of data values
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Highly accurate data value prediction using hybrid predictors
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Confidence estimation for speculation control
Proceedings of the 25th annual international symposium on Computer architecture
Understanding the differences between value prediction and instruction reuse
MICRO 31 Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture
ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
Load-reuse analysis: design and evaluation
Proceedings of the ACM SIGPLAN 1999 conference on Programming language design and implementation
Dynamic removal of redundant computations
ICS '99 Proceedings of the 13th international conference on Supercomputing
Extending Value Reuse to Basic Blocks with Compiler Support
IEEE Transactions on Computers
Register integration: a simple and efficient implementation of squash reuse
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Load and store reuse using register file contents
ICS '01 Proceedings of the 15th international conference on Supercomputing
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Exploiting speculative value reuse using value prediction
CRPIT '02 Proceedings of the seventh Asia-Pacific conference on Computer systems architecture
Exploiting Basic Block Value Locality with Block Reuse
HPCA '99 Proceedings of the 5th International Symposium on High Performance Computer Architecture
Exploring Sub-Block Value Reuse for Superscalar Processors
PACT '00 Proceedings of the 2000 International Conference on Parallel Architectures and Compilation Techniques
The Dynamic Trace Memorization Reuse Technique
PACT '00 Proceedings of the 2000 International Conference on Parallel Architectures and Compilation Techniques
ICPP '99 Proceedings of the 1999 International Conference on Parallel Processing
Load Redundancy Removal through Instruction Reuse
ICPP '00 Proceedings of the Proceedings of the 2000 International Conference on Parallel Processing
The Limits of Speculative Trace Reuse on Deeply Pipelined Processors
SBAC-PAD '03 Proceedings of the 15th Symposium on Computer Architecture and High Performance Computing
A Speculative Trace Reuse Architecture with Reduced Hardware Requirements
SBAC-PAD '06 Proceedings of the 18th International Symposium on Computer Architecture and High Performance Computing
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Trace reuse is a powerful technique to dynamically collapse instructions. Traces, that is, dynamic sequences of instructions, are detected during runtime and their inputs and outputs are stored in a table. The next time the same address is reached and the inputs are the same, this sequence of instructions can be safely bypassed and the same outputs are written in registers and memory. One of the major issues with trace reuse is that all inputs must be ready for the reuse test or the trace cannot be reused. Reuse through Speculation on Traces (RST) adds value prediction to trace reuse, so that traces with inputs that are not ready for early validation can be speculatively reused and validated later in the pipeline. Another important problem is the number of wires that are used to transmit inputs from the reuse table to the reuse test stage, which increases with table associativity and pipeline width. In this paper, we compare the limits of RST with two reuse implementation strategies: one with two reuse tables and high associativity and another with a direct-mapped, unified reuse table. The unified table organisation, considerably simpler to implement, presented a speedup of 1.24 over the baseline with a reduction of less than 4% in performance when compared to the two table approach.