The use of multithreading for exception handling

  • Authors:

  • Craig B. Zilles;Joel S. Emer;Gurindar S. Sohi

  • Affiliations:

  • Computer Sciences Department, University of Wisconsin - Madison, 1210 West Dayton Street, Madison, WI;Alpha Development Group, Compaq Computer Corporation;Computer Sciences Department, University of Wisconsin - Madison, 1210 West Dayton Street, Madison, WI

  • Venue:
  • Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
  • Year:
  • 1999

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Abstract

Common hardware exceptions, when implemented by trapping, unnecessarily serialize program execution in dynamically scheduled superscalar processors. To avoid the consequences of trapping the main program thread, multithreaded CPUs can exploit control and data independence by executing the exception handler in a separate hardware context. The main thread doesn't squash instructions after the excepting instruction, conserving fetch bandwidth and allowing execution of instructions independent of the exception. This leads to earlier branch resolution in the post exception code and additional memory latency tolerance. As a proof of concept, using threads to handle software TLB misses is shown to provide performance approaching that of an aggressive hardware TLB miss handler.