Sequential element design with built-in soft error resilience

  • Authors:

  • Ming Zhang;Subhasish Mitra;T. M. Mak;Norbert Seifert;Nicholas J. Wang;Quan Shi;Kee Sup Kim;Naresh R. Shanbhag;Sanjay J. Patel

  • Affiliations:

  • Intel Corporation, Folsom, CA;Department of Electrical Engineering, Stanford University, Stanford, CA;Intel Corporation, Folsom, CA;Intel Corporation, Folsom, CA;Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, Urbana, IL;Intel Corporation, Folsom, CA;Intel Corporation, Folsom, CA;Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, Urbana, IL;Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, Urbana, IL

  • Venue:
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • Year:
  • 2006

Quantified Score

Hi-index 0.00

Visualization

Abstract

This paper presents a built-in soft error resilience (BISER) technique for correcting radiation-induced soft errors in latches and flip-flops. The presented error-correcting latch and flip-flop designs are power efficient, introduce minimal speed penalty, and employ reuse of on-chip scan design-for-testability and design-for-debug resources to minimize area overheads. Circuit simulations using a sub-90-nm technology show that the presented designs achieve more than a 20-fold reduction in cell-level soft error rate (SER). Fault injection experiments conducted on a microprocessor model further demonstrate that chip-level SER improvement is tunable by selective placement of the presented error-correcting designs. When coupled with error correction code to protect in-pipeline memories, the BISER flip-flop design improves chip-level SER by 10 times over an unprotected pipeline with the flip-flops contributing an extra 7-10.5% in power. When only soft errors in flips-flops are considered, the BISER technique improves chip-level SER by 10 times with an increased power of 10.3%. The error correction mechanism is configurable (i.e., can be turned on or off) which enables the use of the presented techniques for designs that can target multiple applications with a wide range of reliability requirements.