Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Does retiming affect redundancy in sequential circuits?
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Time Redundancy Based Soft-Error Tolerance to Rescue Nanometer Technologies
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Synthesis for Testability by Sequential Redundancy Removal Using Retiming
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
Partial Error Masking to Reduce Soft Error Failure Rate in Logic Circuits
DFT '03 Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Principles of Sequential-Equivalence Verification
IEEE Design & Test
MARS-C: modeling and reduction of soft errors in combinational circuits
Proceedings of the 43rd annual Design Automation Conference
An Analysis Framework for Transient-Error Tolerance
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
Node Mergers in the Presence of Don't Cares
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Enhancing design robustness with reliability-aware resynthesis and logic simulation
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Alpha-particle-induced upsets in advanced CMOS circuits and technology
IBM Journal of Research and Development
Sequential element design with built-in soft error resilience
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Markovian analysis of large finite state machines
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Modeling and Optimization for Soft-Error Reliability of Sequential Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
RALF: reliability analysis for logic faults: an exact algorithm and its applications
Proceedings of the Conference on Design, Automation and Test in Europe
Retiming for Soft Error Minimization Under Error-Latching Window Constraints
Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 0.00 |
State elements are increasingly vulnerable to soft errors due to their decreasing size, and the fact that latched errors cannot be completely eliminated by electrical or timing masking. Most prior methods of reducing the soft-error rate (SER) involve combinational redesign, which tends to add area and decrease testability, the latter a concern due to the prevalence of manufacturing defects. Our work explores the fundamental relations between the SER of sequential circuits and their testability in scan mode, and appears to be the first to improve both through retiming. Our retiming methodology relocates registers so that 1) registers become less observable with respect to primary outputs, thereby decreasing overall SER, and 2) combinational nodes become more observable with respect to registers (but not with respect to primary outputs), thereby increasing scan-testability. We present experimental results which show an average decrease of 42% in the SER of latches, and an average improvement of 31% random-pattern testability.