DAC '93 Proceedings of the 30th international Design Automation Conference
Classification of Faults in Synchronous Sequential Circuits
IEEE Transactions on Computers
One-Pass Redundancy Identification and Removal
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
On Achieving Complete Testability of Synchronous Sequential Circuits with Synchronizing Sequences
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Resynthesis for sequential circuits designed with a specified initial state
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
8.3 On Removing Redundant Faults in Synchronous Sequential Circuits
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Improving testability and soft-error resilience through retiming
Proceedings of the 46th Annual Design Automation Conference
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The existence of sequential redundancy will degrade testability of sequential circuits. By using retiming which rearranges flip-flops, some sequential redundancy are converted into combinational redundancy, which can be easily identified and removed by a combinational test generation technique. In this paper retiming is utilized for two purposes: one is for finding sequential redundancy and another is for reducing the number of flip-flops. Applying retiming and redundancy removal techniques concurrently, testability of sequential circuits will be enhanced. Experimental results for ISCAS'89 benchmark circuits show effectiveness of this method to optimize the circuits.