Accurate Reliability Evaluation and Enhancement via Probabilistic Transfer Matrices
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Cost-effective radiation hardening technique for combinational logic
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Enhancing design robustness with reliability-aware resynthesis and logic simulation
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A soft error analysis tool for high-speed digital designs
Proceedings of the 2nd international conference on Ubiquitous information management and communication
On the role of timing masking in reliable logic circuit design
Proceedings of the 45th annual Design Automation Conference
Adopting the Drowsy Technique for Instruction Caches: A Soft Error Perspective
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Improving testability and soft-error resilience through retiming
Proceedings of the 46th Annual Design Automation Conference
Signature-based SER analysis and design of logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Partitioning techniques for partially protected caches in resource-constrained embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Soft error modeling and remediation techniques in ASIC designs
Microelectronics Journal
Detecting errors using multi-cycle invariance information
Proceedings of the Conference on Design, Automation and Test in Europe
SETmap: a soft error tolerant mapping algorithm for FPGA designs with low power
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Retiming for Soft Error Minimization Under Error-Latching Window Constraints
Proceedings of the Conference on Design, Automation and Test in Europe
SOP restructuring by exploiting don't cares
Microprocessors & Microsystems
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A new methodology for designing logic circuits with partial error masking is described. The key idea is to exploit the asymmetric soft error susceptibility of nodes in a logic circuit by targeting the error masking capability towards the nodes with the highest soft error susceptibility to achieve cost-effective tradeoffs between overhead and reduction in the soft error failure rate. Such techniques can be used in cost-sensitive high volume main-stream applications to satisfy soft error failure rate requirements at minimum cost. Two reduction heuristics, cluster sharing reduction and dominant value reduction, are used to reduce the soft error failure rate significantly with a fraction of the overhead required for conventional TMR.