Multi-level logic optimization by implication analysis
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
FIRE: a fault-independent combinational redundancy identification algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reducing power dissipation after technology mapping by structural transformations
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Timing optimization by an improved redundancy addition and removal technique
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Symbolic computation of logic implications for technology-dependent low-power synthesis
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
A high-frequency custom CMOS S/390 microprocessor
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
Estimation of maximum current envelope for power bus analysis and design
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Multi-node static logic implications for redundancy identification
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Dual use of superscalar datapath for transient-fault detection and recovery
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
False-noise analysis using logic implications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
FoCs: Automatic Generation of Simulation Checkers from Formal Specifications
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Static logic implication with application to redundancy identification
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
14.3 Synthesis of Circuits with Low-Cost Concurrent Error Detection Based on Bose-Lin Codes
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
WHICH CONCURRENT ERROR DETECTION SCHEME TO CHOOSE?
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Partial Error Masking to Reduce Soft Error Failure Rate in Logic Circuits
DFT '03 Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Cost-Driven Selection of Parity Trees
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Opportunistic Transient-Fault Detection
Proceedings of the 32nd annual international symposium on Computer Architecture
Assertion Checkers in Verification, Silicon Debug and In-Field Diagnosis
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Enhancing design robustness with reliability-aware resynthesis and logic simulation
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A low-cost concurrent error detection technique for processor control logic
Proceedings of the conference on Design, automation and test in Europe
Zchaff2004: an efficient SAT solver
SAT'04 Proceedings of the 7th international conference on Theory and Applications of Satisfiability Testing
Logic synthesis of multilevel circuits with concurrent error detection
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Compacting test vector sets via strategic use of implications
Proceedings of the 2009 International Conference on Computer-Aided Design
Improving the testability and reliability of sequential circuits with invariant logic
Proceedings of the 20th symposium on Great lakes symposium on VLSI
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Ensuring reliable computation at the nanoscale requires mechanisms to detect and correct errors during normal circuit operation. In this paper we propose a method for designing efficient online error detection schemes for circuits based on the identification of invariant relationships in hardware. More specifically, we present a technique that automatically identifies multi-cycle gate-level invariant relationships---where no knowledge of high-level behavioral constraints is required to identify the relationships---and generates the checker logic that verifies these implications. Our results show that cross-cycle implications are particularly useful in discovering difficult-to-detect errors near latch boundaries, and can have a significant impact on boosting error detection rates.