An Experimental Chip to Evaluate Test Techniques: Experiment Results
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
WHICH CONCURRENT ERROR DETECTION SCHEME TO CHOOSE?
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Test Point Insertion that Facilitates ATPG in Reducing Test Time and Data Volume
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Vector restoration based static compaction of test sequences for synchronous sequential circuits
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Reducing Fault Latency in Concurrent On-Line Testing by Using Checking Functions over Internal Lines
DFT '04 Proceedings of the Defect and Fault Tolerance in VLSI Systems, 19th IEEE International Symposium
A low-cost concurrent error detection technique for processor control logic
Proceedings of the conference on Design, automation and test in Europe
Compacting test vector sets via strategic use of implications
Proceedings of the 2009 International Conference on Computer-Aided Design
A cost effective approach for online error detection using invariant relationships
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Detecting errors using multi-cycle invariance information
Proceedings of the Conference on Design, Automation and Test in Europe
Using implications to choose tests through suspect fault identification
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
| Hi-index | 0.00 |
In this paper, we propose the use of logic implications to enhance online error detection capabilities and to improve the testing efficiency of an integrated circuit. These logic implications are implemented in hardware and help to verify that expected invariant circuit relationships are satisfied during field operation. Thus, any implication violation will indicate the presence of an error due to some faulty circuit behavior. In addition, checking these logic implications in hardware will create additional circuit outputs, which may be useful for compacting $n$-detect test sets. Our results show that logic implications can provide significant error detection and test pattern count reduction with very limited hardware overhead.