Improving the testability and reliability of sequential circuits with invariant logic
Proceedings of the 20th symposium on Great lakes symposium on VLSI
A cost effective approach for online error detection using invariant relationships
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Using implications to choose tests through suspect fault identification
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
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We describe a method to reduce the fault latency, i.e., the time it takes to detect a fault after it occurs, during concurrent on-line testing.A high fault latency can negatively affect the fault coverage in various ways.The fault latency is reduced by using what we call checking functions.A checking funtion cf_i expresses the function of a line g_i in the circuit as a function of one or more other lines.During concurrent on-line testing, the value of g_i is compared to the value of cf_i.A mismatch indicates the presence of a fault.The advantage of checking functions is that they only use lines that already exist in the circuit.We demonstrate that benchmark circuits have large numbers of checking functions to choose from.We also demonstrate the increase in fault coverage and the reductions in faultdetection times possible by using checking functions.