A low-cost concurrent error detection technique for processor control logic

Authors:
Ramtilak Vemu;Abhijit Jas;Jacob A. Abraham;Rajesh Galivanche;Srinivas Patil
Affiliations:
University of Texas at Austin;University of Texas at Austin;Design and Technology Solutions, Intel Corporation;Design and Technology Solutions, Intel Corporation;Design and Technology Solutions, Intel Corporation
Venue:
Proceedings of the conference on Design, automation and test in Europe
Year:
2008

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Abstract

This paper presents a concurrent error detection technique targeted towards control logic in a processor with emphasis on low area overhead. Rather than detect all modeled transient faults, the technique selects faults which have a high probability of causing damage to the architectural state of the processor and protects the circuit against these faults. Fault detection is achieved through a series of assertions. Each assertion is an implication from inputs to the outputs of a combinational circuit. Fault simulation experiments performed on control logic modules of an industrial processor suggest that high reduction in damage causing faults can be achieved with a low overhead.