A Formal Approach to On-Line Monitoring of Digital VLSI Circuits: Theory, Design and Implementation
Journal of Electronic Testing: Theory and Applications
A low-cost concurrent error detection technique for processor control logic
Proceedings of the conference on Design, automation and test in Europe
Circuit Level Concurrent Error Detection in FSMs
Journal of Electronic Testing: Theory and Applications
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We propose a methodology for non-intrusive design ofconcurrently self-testable FSMs. The proposed method issimilar to duplication, wherein a replica of the originalFSM acts as a predictor that immediately detects potentialfaults by comparison to the original FSM. However, insteadof duplicating the complete FSM, the proposed methodreplicates only a minimal portion adequate to detect all possiblefaults, yet at the cost of introducing potential fault detectionlatency. Furthermore, in contrast to concurrent errordetection approaches, which presume the ability to resynthesizethe FSM and exploit parity-based state encoding,the proposed method is non-intrusive and does not interferewith the encoding and implementation of the original FSM.Experimental results on FSMs of various sizes and densitiesindicate that the proposed method detects 100% of the faultswith very low average fault detection latency. Furthermore,a hardware overhead reduction of up to 33% is achieved, ascompared to duplication-based concurrent error detection.