Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Avoiding the state explosion problem in temporal logic model checking
PODC '87 Proceedings of the sixth annual ACM Symposium on Principles of distributed computing
Optimized Synthesis of Concurrently Checked Controllers
IEEE Transactions on Computers
Finite-state machine synthesis for continuous, concurrent error detection using signature-invariant monitoring
High-level area and power estimation for VLSI circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
On-Line Testing for VLSI—A Compendium of Approaches
Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
Design of VHDL-based totally self-checking finite-state machine and data-path descriptions
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Switching and Finite Automata Theory: Computer Science Series
Switching and Finite Automata Theory: Computer Science Series
Self-Checking Design in Eastern Europe
IEEE Design & Test
Alternative Approaches to Fault Detection in FSMs
Proceedings of the The IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
An Effective BIST Scheme for Datapaths
Proceedings of the IEEE International Test Conference on Test and Design Validity
Non-Intrusive Design of Concurrently Self-Testable FSMs
ATS '02 Proceedings of the 11th Asian Test Symposium
14.3 Synthesis of Circuits with Low-Cost Concurrent Error Detection Based on Bose-Lin Codes
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Programmable Embedded Self-Testing Checkers for All-Unidirectional Error-Detecting Codes
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Test Point Insertion for Compact Test Sets
ITC '00 Proceedings of the 2000 IEEE International Test Conference
New Self-Checking Circuits by Use of Berger-Codes
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
A New Method for Concurrent Checking by Use of a 1-out-of-4 Code
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
Finite State Machine Synthesis with Concurrent Error Detection
ITC '99 Proceedings of the 1999 IEEE International Test Conference
On Concurrent Error Detection with Bounded Latency in FSMs
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Logic synthesis of multilevel circuits with concurrent error detection
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On-line and off-line testing with shared resources: a new BIST approach
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This work is concerned with the development of algorithms and CAD tools for the design of digital circuits with on line monitoring capability. The Theory of Fault Detection and Diagnosis available in the literature on Discrete Event Systems has been adopted for on-line detection of stuck-at faults in Digital Circuits. Efficient computational techniques to deal with very large state spaces based on Ordered Binary Decision Diagrams and Abstraction have been proposed. Based on these a CAD tool has been developed that can provide a fully automated flow for design of circuits with on-line test capability without the requirement of any modification to the core. The tool can handle generic digital circuits with cell count as high as 15,000 and having the order of 2500 states. This is believed to be an improvement of an order of magnitude over results presented in the literature. This methodology enables the designer to tradeoff fault coverage and detection latency against area and power overhead. The design flow using the CAD tool developed is described and results for design of on-line detectors for various ISCAS89 benchmark circuits are provided. The methodology is further validated by design, fabrication, and testing of an ASIC in 0.18 驴 technology.