High-level area and power estimation for VLSI circuits

Authors:
Mahadevamurty Nemani;Farid N. Najm
Affiliations:
ECE Dept. and Coordinated Science Lab., University of Illinois at Urbana-Champaign, Urbana, Illinois;ECE Dept. and Coordinated Science Lab., University of Illinois at Urbana-Champaign, Urbana, Illinois
Venue:
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Year:
1997

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Abstract

This paper addresses the problem of computing the area complexity of a multi-output combinational logic circuit, given only its functional description, i.e., Boolean equations, where area complexity is measured in terms of the number of gates required for an optimal multi-level implementation of the combinational logic. The proposed area model is based on transforming the given multi-output Boolean function description into an equivalent single-output function. The model is empirical, and results demonstrating its feasibility and utility are presented. Also, a methodology for converting the gate count estimates, obtained from the area model, into capacitance estimates is presented. High-level power estimates based on the total capacitance estimates and average activity estimates are also presented.