Introduction to operations research, 4th ed.
Introduction to operations research, 4th ed.
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Fast performance-driven optimization for buffered clock trees based on Lagrangian relaxation
DAC '96 Proceedings of the 33rd annual Design Automation Conference
An exact algorithm for low power library-specific gate re-sizing
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Post global routing crosstalk risk estimation and reduction
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
High-level area and power estimation for VLSI circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Efficient coupled noise estimation for on-chip interconnects
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Design methodologies for noise in digital integrated circuits
DAC '98 Proceedings of the 35th annual Design Automation Conference
Timing and crosstalk driven area routing
DAC '98 Proceedings of the 35th annual Design Automation Conference
Layout techniques for minimizing on-chip interconnect self inductance
DAC '98 Proceedings of the 35th annual Design Automation Conference
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal reliable crosstalk-driven interconnect optimization
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Power supply design parameters prediction for high performance IC design flows
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
Power Supply Design Parameters for Switching-Noise Control in Deep-Submicron Circuits Design Flows
Analog Integrated Circuits and Signal Processing
Crosstalk-Constrained Performance Optimization by Using Wire Sizing and Perturbation
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Timing modeling and optimization under the transmission line model
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Statistical circuit optimization considering device andinterconnect process variations
Proceedings of the 2007 international workshop on System level interconnect prediction
An efficient algorithm for statistical circuit optimization using Lagrangian relaxation
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |