Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
On thermal effects in deep sub-micron VLSI interconnects
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Impact of interconnect variations on the clock skew of a gigahertz microprocessor
Proceedings of the 37th Annual Design Automation Conference
Analysis and optimization of thermal issues in high-performance VLSI
Proceedings of the 2001 international symposium on Physical design
Low Power Digital CMOS Design
Introduction to Algorithms
Partition-driven standard cell thermal placement
Proceedings of the 2003 international symposium on Physical design
Convex Optimization
Variational delay metrics for interconnect timing analysis
Proceedings of the 41st annual Design Automation Conference
Novel sizing algorithm for yield improvement under process variation in nanometer technology
Proceedings of the 41st annual Design Automation Conference
A New Statistical Optimization Algorithm for Gate Sizing
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
A New Method for Design of Robust Digital Circuits
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
An efficient algorithm for statistical minimization of total power under timing yield constraints
Proceedings of the 42nd annual Design Automation Conference
The impact of device parameter variations on the frequency and performance of VLSI chips
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Statistical analysis and optimization in the presence of gate and interconnect delay variations
Proceedings of the 2006 international workshop on System-level interconnect prediction
Cell-level placement for improving substrate thermal distribution
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Crosstalk-driven interconnect optimization by simultaneous gate and wire sizing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An efficient algorithm for statistical circuit optimization using Lagrangian relaxation
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
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Process Variation has become a crucial challenge on both interconnect delay and reliability of nanometer integrated circuit designs. Furthermore, the dramatic increase of power consumption and integration density has led to high operating temperature. Temperature, as well as electromigration (EM) and power, also significantly affects the delay and reliability of interconnects. Considering process variation, we present the first work to use statistical methods to optimize the circuit area under timing, thermal and power constraints by gate and interconnect sizing optimization. We model the problem as a second-order conic program and solve it with the interior-point method. Experimental results show that our statistical algorithm can find desired solutions that satisfy all delay, power, and thermal constraints. Our statistical algorithm on average improves the circuit areas by respective 51.12%, 39.21%, and 25.60% with 70%, 84.1%, and 99.9% yields after wire and gate sizing.