Crosstalk noise optimization by post-layout transistor sizing
Proceedings of the 2002 international symposium on Physical design
Crosstalk noise estimation for noise management
Proceedings of the 39th annual Design Automation Conference
Signal integrity management in an SoC physical design flow
Proceedings of the 2003 international symposium on Physical design
Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Crosstalk Minimization in Logic Synthesis for PLA
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Enhancing Signal Integrity through a Low-Overhead Encoding Scheme on Address Buses
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 11 - Volume 12
Geometric programming for circuit optimization
Proceedings of the 2005 international symposium on Physical design
Gate sizing for crosstalk reduction under timing constraints by Lagrangian relaxation
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
True crosstalk aware incremental placement with noise map
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Optimal partitioned fault-tolerant bus layout for reducing power in nanometer designs
Proceedings of the 2006 international symposium on Physical design
Reliable crosstalk-driven interconnect optimization
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Post-Layout Gate Sizing for Interconnect Delay and Crosstalk Noise Optimization
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Proceedings of the 41st annual Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computers
Crosstalk minimization in logic synthesis for PLAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Statistical circuit optimization considering device andinterconnect process variations
Proceedings of the 2007 international workshop on System level interconnect prediction
Digital Circuit Optimization via Geometric Programming
Operations Research
Power optimal MTCMOS repeater insertion for global buses
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Timing-driven row-based power gating
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Elmor model-based algorithm to select optimal connections on the clock tree
Automation and Remote Control
A data capturing method for buses on chip
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Fast and efficient lagrangian relaxation-based discrete gate sizing
Proceedings of the Conference on Design, Automation and Test in Europe
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Noise, as well as area, delay, and power, is one of the most important concerns in the design of deep submicrometer integrated circuits. Currently existing algorithms do not handle simultaneous switching conditions of signals for noise minimization. In this paper, we model not only physical coupling capacitance, but also simultaneous switching behavior for noise optimization. Based on Lagrangian relaxation, we present an algorithm which can optimally solve the simultaneous noise, area, delay, and power optimization problem by sizing circuit components. Our algorithm, with linear memory requirement and linear runtime, is very effective and efficient. For example, for a circuit of 6144 wires and 3512 gates, our algorithm solves the simultaneous optimization problem using only 2.1-MB memory and 19.4-min runtime to achieve the precision of within 1% error on a SUN Spare Ultra-I workstation