Rectilinear Steiner trees with minimum Elmore delay
DAC '94 Proceedings of the 31st annual Design Automation Conference
EWA: exact wiring-sizing algorithm
Proceedings of the 1997 international symposium on Physical design
Closed form solutions to simultaneous buffer insertion/sizing and wire sizing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
Crosstalk-driven interconnect optimization by simultaneous gate and wire sizing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Wire width planning for interconnect performance optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal wiresizing under Elmore delay model
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Consideration was given to two formulations of the problem of selecting the optimal types of interconnections on the edges of the given rooted tree along which the signal is transmitted from the root to the terminals. The time interval during which the signal must be received was defined for each terminal. The time of signal propagation which depends on the interconnections used on all tree edges was calculated using the Elmor formulas. It was required to select interconnections of the minimal total capacitance such that the times of signal arrival to each terminal be admissible. Pseudopolynomial algorithms of dynamic programming were proposed to determine optimal solutions of the examined problems.