Interconnect width selection for deep submicron designs using the table lookup method
Proceedings of the 2004 international workshop on System level interconnect prediction
Integrating buffer planning with floorplanning for simultaneous multi-objective optimization
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Geometric programming for circuit optimization
Proceedings of the 2005 international symposium on Physical design
Wire sizing with scattering effect for nanoscale interconnection
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Proceedings of the 41st annual Design Automation Conference
Design and verification of high-speed VLSI physical design
Journal of Computer Science and Technology
Digital Circuit Optimization via Geometric Programming
Operations Research
Improved performance and yield with chip master planning design methodology
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Elmor model-based algorithm to select optimal connections on the clock tree
Automation and Remote Control
Hi-index | 0.03 |
In this paper, we study wire width planning for interconnect performance optimization in an interconnect-centric design flow. We first propose some simplified, yet near-optimal wire sizing schemes, using only one or two discrete wire widths. Our sensitivity study on wire sizing optimization further suggests that there exists a small set of "globally" optimal wire widths for a range of interconnects. We develop general and efficient methods for computing such a "globally" optimal wire width design and show rather surprisingly that using only two "predesigned" widths for each metal layer, we are still able to achieve close to optimal performance compared with that by using many possible widths, not only for one fixed length, but also for all wire lengths assigned at each metal layer. Our wire width planning can consider different design objectives and wire length distributions. Moreover, our method has a predictable small amount of errors compared with optimal solutions. We expect that our simplified wire sizing schemes and wire width planning methodology will be very useful for better design convergence and simpler routing architectures