Interconnect width selection for deep submicron designs using the table lookup method

Authors:
Mandeep Bamal;Evelyn Grossar;Michele Stucchi;Karen Maex
Affiliations:
IMEC, Leuven, Belgium and Doctoral Student at Katholieke Universiteit Leuven, Belgium;IMEC, Leuven, Belgium and Doctoral Student at Katholieke Universiteit Leuven, Belgium;IMEC, Leuven, Belgium and Professor at the Katholieke Universiteit Leuven, Belgium;IMEC, Leuven, Belgium and Professor at the Katholieke Universiteit Leuven, Belgium
Venue:
Proceedings of the 2004 international workshop on System level interconnect prediction
Year:
2004

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Abstract

Interconnect width sizing is critical in deep submicron designs to reduce the overall delay. In this paper we present an algorithm for optimal interconnect width selection from a predetermined and precharacterized wire width metric. This algorithm uses a 4-dimensional lookup table approach based on "O'Brien, Savarino" π model for the interconnect load. This methodology can easily be integrated into the existing design tools since this methodology lies in the middle of the postplacement and prerouting step of the physical design flow. We will explore a trade-off between delay and power dissipation for different widths and a comparison will also be made with the ITRS design rules.