Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique
Proceedings of the 2002 international symposium on Physical design
Optimum wire sizing of RLC interconnect with repeaters
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Interconnect Delay Minimization Using a Novel Pre-Mid-Post Buffer Strategy
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Interconnect width selection for deep submicron designs using the table lookup method
Proceedings of the 2004 international workshop on System level interconnect prediction
Optimum wire sizing of RLC interconnect with repeaters
Integration, the VLSI Journal
The coming of age of physical synthesis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Fast interconnect synthesis with layer assignment
Proceedings of the 2008 international symposium on Physical design
A polynomial time approximation scheme for timing constrained minimum cost layer assignment
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Proceedings of the 2009 international symposium on Physical design
A faster approximation scheme for timing driven minimum cost layer assignment
Proceedings of the 2009 international symposium on Physical design
A fully polynomial-time approximation scheme for timing-constrained minimum cost layer assignment
IEEE Transactions on Circuits and Systems II: Express Briefs
Wire synthesizable global routing for timing closure
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Design of a novel differential on-chip wave-pipelined serial interconnect with surfing
Microprocessors & Microsystems
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Interconnect synthesis techniques, such as wire sizing and buffer insertion/sizing, have proven to be critical for reducing interconnect delays in deep submicron design. Consequently, the past few years have seen several works that study buffer insertion, wire sizing, and their simultaneous optimization. For long interconnect, wire tapering, i.e., reducing the wire width as the distance from the driver increases, can yield better solutions than uniform wire sizing. However, despite its obvious benefits, tapering is not widely used in practice since it is difficult to integrate into a coherent routing methodology. This paper studies the benefits of wire sizing with tapering when combined with buffer insertion. We first present a theoretical result that shows wire tapering is at most 3.5% faster than uniform wire sizing when maximal buffer insertion is applied. We then present detailed experiments that support this result. Consequently, we conclude that it is generally not worthwhile to perform tapering for signal nets. Finally, we present a general formulation and optimal polynomial time algorithm for simultaneous wire sizing and buffer insertion that forbids wire tapering, but incorporates layer assignment and wire spacing