Optimum wire sizing of RLC interconnect with repeaters

Authors:
Magdy A. El-Moursy;Eby G. Friedman
Affiliations:
University of Rochester, Rochester, NY;University of Rochester, Rochester, NY
Venue:
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Year:
2003

Citing 10
Cited 9

A unified design methodology for CMOS tapered buffers

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Effects of inductance on the propagation delay and repeater insertion in VLSI circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Figures of merit to characterize the importance of on-chip inductance

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Minimum power and area n-tier multilevel interconnect architectures using optimal repeater insertion

ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Interconnect-Dominated VLSI Design

ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
Effective On-chip Inductance Modeling for Multiple Signal Lines and Application on Repeater Insertion

ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
High-speed clock network sizing optimization based on distributed RC and lossy RLC interconnect models

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Interconnect synthesis without wire tapering

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Analysis of on-chip inductance effects for distributed RLC interconnects

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal wiresizing under Elmore delay model

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Predictions of CMOS compatible on-chip optical interconnect

Proceedings of the 2005 international workshop on System level interconnect prediction
Optimum wire sizing of RLC interconnect with repeaters

Integration, the VLSI Journal
On-Chip Communication Architectures: System on Chip Interconnect

On-Chip Communication Architectures: System on Chip Interconnect
Wire shaping of RLC interconnects

Integration, the VLSI Journal
Pattern-matching-based X-architecture zero-skew clock tree construction with X-Flip technique and via delay consideration

Integration, the VLSI Journal
Evaluating carbon nanotube global interconnects for chip multiprocessor applications

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power characteristics of inductive interconnect

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Differential current-sensing for on-chip interconnects

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy and performance models for synchronous and asynchronous communication

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

Repeaters are often used to drive high impedance interconnects. These lines have become highly inductive which can affect signal behavior in long interconnects. The line inductance should, therefore, be considered in determining the optimum number and size of the repeaters driving a line. A tradeoff exists, however, between the transient power dissipation and the minimum propagation delay in sizing long interconnects driven by repeaters. Optimizing the line width to achieve the minimum power delay product, however, can satisfy current high speed, low power design objectives. A reduction in power of 65% and delay of 97% is achieved for an example repeater system.