A sub-CV2 pad driver with 10 ns transition time
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Short circuit power estimation of static CMOS circuits
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Optimum wire sizing of RLC interconnect with repeaters
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Shielding effect of on-chip interconnect inductance
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Interconnect-aware high-level synthesis for low power
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Analysis of buck converters for on-chip integration with a dual supply voltage microprocessor
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Predictions of CMOS compatible on-chip optical interconnect
Proceedings of the 2005 international workshop on System level interconnect prediction
Optimum wire sizing of RLC interconnect with repeaters
Integration, the VLSI Journal
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Predictions of CMOS compatible on-chip optical interconnect
Integration, the VLSI Journal
Analytical Model for the CMOS Short-Circuit Power Dissipation
Integrated Computer-Aided Engineering
Three-dimensional Integrated Circuit Design
Three-dimensional Integrated Circuit Design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Simultaneous shield and repeater insertion
Proceedings of the 19th ACM Great Lakes symposium on VLSI
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Shielding effect of on-chip interconnect inductance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
In this paper, the various disparate approaches to CMOS tapered buffer design are unified into an integrated design methodology. Circuit speed, power dissipation, physical area, and system reliability are the four performance criteria of concern in tapered buffers, and each places a separate, often conflicting, constraint on the design of a tapered buffer. Enhanced short-channel tapered buffer design equations are presented for propagation delay and power dissipation, as well as a new split-capacitor model of hot-carrier reliability of tapered buffers and a two-component physical area model. Each performance criterion is individually investigated and analyzed with respect to the number of stages and tapering factor, and the interaction of the four criteria is examined to develop both a qualitative and a quantitative understanding of the various design tradeoffs. The creation of process dependent look-up tables for optimal buffer design is described, and a methodology to apply these look-up tables to application-specific tapered buffers for both unconstrained and constrained systems is developed.