Predictions of CMOS compatible on-chip optical interconnect

Authors:
Guoqing Chen;Hui Chen;Mikhail Haurylau;Nicholas Nelson;Philippe M. Fauchet;Eby G. Friedman;David Albonesi
Affiliations:
University of Rochester, Rochester, NY;University of Rochester, Rochester, NY;University of Rochester, Rochester, NY;University of Rochester, Rochester, NY;University of Rochester, Rochester, NY;University of Rochester, Rochester, NY;Cornell University, Ithaca, NY
Venue:
Proceedings of the 2005 international workshop on System level interconnect prediction
Year:
2005

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Abstract

Interconnect has become a primary bottleneck in integrated circuit design. As CMOS technology is scaled, it will become increasingly difficult for conventional copper interconnect to satisfy the design requirements of delay, power, bandwidth, and noise. On-chip optical interconnect has been considered as a potential substitute for electrical interconnect in the past two decades. In this paper, predictions of the performance of CMOS compatible optical devices are made based on current state-of-art optical technologies. Electrical and optical interconnects are compared for various design criteria based on these predictions. The critical dimensions beyond which optical interconnect becomes advantageous over electrical interconnect are shown to be approximately one tenth of the chip edge length at the 22 nm technology node.