Predictions of CMOS compatible on-chip optical interconnect
Proceedings of the 2005 international workshop on System level interconnect prediction
Optical routing for 3D system-on-package
Proceedings of the conference on Design, automation and test in Europe: Proceedings
OIL: a nano-photonics optical interconnect library for a new photonic networks-on-chip architecture
Proceedings of the 11th international workshop on System level interconnect prediction
OIL: a nano-photonics optical interconnect library for a new photonic networks-on-chip architecture
Proceedings of the 11th international workshop on System level interconnect prediction
Logic synthesis for integrated optics
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
System-level modeling and analysis of thermal effects in optical networks-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this work, we present a new optical routing framework, O-Router for future low-power on-chip optical interconnect integration utilizing silicon compatible nano-photonic devices. We formulate the optical layer routing problem as the minimization of total on-chip optical modulator cost (laser power consumption) with Integer Linear Programming technique under various detection constraints. Key techniques for variable number reduction and routing speedup are also explored and utilized. O-Router is tested on optical netlist benchmarks modified from top global nets of ISPD98/08 routing benchmarks. O-Router experimental results are compared with conventional minimum spanning tree algorithm, demonstrating an average of over 50% improvement in terms of total on-chip optical layer power reduction.