Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Networks on Chip: A New Paradigm for Systems on Chip Design
Proceedings of the conference on Design, automation and test in Europe
Temperature-aware microarchitecture: Modeling and implementation
ACM Transactions on Architecture and Code Optimization (TACO)
On the Design of a Photonic Network-on-Chip
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
System level assessment of an optical NoC in an MPSoC platform
Proceedings of the conference on Design, automation and test in Europe
ORB: an on-chip optical ring bus communication architecture for multi-processor systems-on-chip
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics
HOTI '08 Proceedings of the 2008 16th IEEE Symposium on High Performance Interconnects
A Nanophotonic Interconnect for High-Performance Many-Core Computation
HOTI '08 Proceedings of the 2008 16th IEEE Symposium on High Performance Interconnects
Analysis of challenges for on-chip optical interconnects
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Firefly: illuminating future network-on-chip with nanophotonics
Proceedings of the 36th annual international symposium on Computer architecture
Phastlane: a rapid transit optical routing network
Proceedings of the 36th annual international symposium on Computer architecture
On-Chip photonic interconnects for scalable multi-core architectures
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
O-Router: an optical routing framework for low power on-chip silicon nano-photonic integration
Proceedings of the 46th Annual Design Automation Conference
Architecture-level thermal characterization for multicore microprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Crosstalk noise and bit error rate analysis for optical network-on-chip
Proceedings of the 47th Design Automation Conference
A Hierarchical Hybrid Optical-Electronic Network-on-Chip
ISVLSI '10 Proceedings of the 2010 IEEE Annual Symposium on VLSI
A low-power fat tree-based optical network-on-chip for multiprocessor system-on-chip
Proceedings of the Conference on Design, Automation and Test in Europe
A NoC Traffic Suite Based on Real Applications
ISVLSI '11 Proceedings of the 2011 IEEE Computer Society Annual Symposium on VLSI
Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip
ISVLSI '11 Proceedings of the 2011 IEEE Computer Society Annual Symposium on VLSI
Reliability Modeling and Management of Nanophotonic On-Chip Networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The performance of multiprocessor systems, such as chip multiprocessors (CMPs), is determined not only by individual processor performance, but also by how efficiently the processors collaborate with one another. It is the communication architecture that determines the collaboration efficiency on the hardware side. Optical networks-on-chip (ONoCs) are emerging communication architectures that can potentially offer ultra-high communication bandwidth and low latency to multiprocessor systems. Thermal sensitivity is an intrinsic characteristic of photonic devices used by ONoCs as well as a potential issue. This paper systematically modeled and quantitatively analyzed the thermal effects in ONoCs. We used an 8 × 8 mesh-based ONoC as a case study and evaluated the impacts of thermal effects in the average power efficiency for real MPSoC applications. We revealed three important factors regarding ONoC power efficiency under temperature variations, and proposed several techniques to reduce the temperature sensitivity of ONoCs. These techniques include the optimal initial setting of microresonator resonant wavelength, increasing the 3-dB bandwidth of optical switching elements by parallel coupling multiple microresonators, and the use of passive-routing optical router Crux to minimize the number of switching stages in mesh-based ONoCs. We gave a mathematical analysis of periodically parallel coupling of multiple microresonators and show that the 3-dB bandwidth of optical switching elements can be widened nearly linearly with the ring number. Evaluation results for different real MPSoC applications show that, on the basis of thermal tuning, the optimal device setting improves the average power efficiency by 54% to 1.2 pJ/bit when chip temperature reaches 85 C. The findings in this paper can help support the further development of this emerging technology.