A Hierarchical Hybrid Optical-Electronic Network-on-Chip

Authors:
Kwai Hung Mo;Yaoyao Ye;Xiaowen Wu;Wei Zhang;Weichen Liu;Jiang Xu
Affiliations:
-;-;-;-;-;-
Venue:
ISVLSI '10 Proceedings of the 2010 IEEE Annual Symposium on VLSI
Year:
2010

Citing 0
Cited 4

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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A shortest path adaptive routing technique for minimizing path collisions in hybrid optical network-on-chip

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A formal study on topology and floorplan characteristics of mesh and torus-based optical networks-on-chip

Microprocessors & Microsystems

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Abstract

Network-on-chip (NoC) can improve the performance, power efficiency, and scalability of multiprocessor system-on-chip (MPSoC). However, traditional NoCs using metallic interconnects consume significant amount of power to deliver even higher communication bandwidth required in the near future. Optical NoCs are based on CMOS-compatible optical waveguides and micro resonators, and promise significant bandwidth and power advantages. In this paper, we propose a hybrid optical mesh NoC, HOME, which utilizes optical waveguides as well as metallic interconnects in a hierarchical manner. HOME employs a new set of protocols to improve the network throughput and latency. We compared HOME with a matched optical mesh NoC for a 64-core MPSoC in 45nm, using SPICE simulations and our cycle-accurate multi-objective NoC simulation platform, MoLab. Comparing with the optical mesh NoC, HOME uses 75% less optical/electronic interfaces and laser diodes. Simulation results show that HOME achieves 17% higher throughput and 40% less latency while consuming 42% less power.