The turn model for adaptive routing
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
The Odd-Even Turn Model for Adaptive Routing
IEEE Transactions on Parallel and Distributed Systems
GOAL: a load-balanced adaptive routing algorithm for torus networks
Proceedings of the 30th annual international symposium on Computer architecture
Networks on Chip: A New Paradigm for Systems on Chip Design
Proceedings of the conference on Design, automation and test in Europe
DyAD: smart routing for networks-on-chip
Proceedings of the 41st annual Design Automation Conference
DyXY: a proximity congestion-aware deadlock-free dynamic routing method for network on chip
Proceedings of the 43rd annual Design Automation Conference
Predictions of CMOS compatible on-chip optical interconnect
Integration, the VLSI Journal
On the Design of a Photonic Network-on-Chip
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
System level assessment of an optical NoC in an MPSoC platform
Proceedings of the conference on Design, automation and test in Europe
Photonic NoC for DMA Communications in Chip Multiprocessors
HOTI '07 Proceedings of the 15th Annual IEEE Symposium on High-Performance Interconnects
Traffic-Balanced Routing Algorithm for Irregular Mesh-Based On-Chip Networks
IEEE Transactions on Computers
A Low-power Low-cost Optical Router for Optical Networks-on-Chip in Multiprocessor Systems-on-Chip
ISVLSI '09 Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI
GCIS '09 Proceedings of the 2009 WRI Global Congress on Intelligent Systems - Volume 03
EDXY - A low cost congestion-aware routing algorithm for network-on-chips
Journal of Systems Architecture: the EUROMICRO Journal
Crosstalk noise and bit error rate analysis for optical network-on-chip
Proceedings of the 47th Design Automation Conference
A Hierarchical Hybrid Optical-Electronic Network-on-Chip
ISVLSI '10 Proceedings of the 2010 IEEE Annual Symposium on VLSI
A low-power fat tree-based optical network-on-chip for multiprocessor system-on-chip
Proceedings of the Conference on Design, Automation and Test in Europe
A Torus-Based Hierarchical Optical-Electronic Network-on-Chip for Multiprocessor System-on-Chip
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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Hybrid optical network-on-chip (HONoC) is a promising alternative to all-electrical NoC whose capability in the performance and the power consumption is facing ultimate physical limitation. However, the latency unfairness problem and the associated performance degradation due to the circuit switched characteristic of HONoC must be resolved. In this paper, we propose a new shortest path adaptive routing technique for HONoC by exploiting an elaborate rollback scheme and a rapid flow control method to promote the fast routing path setup and the parallel data transfers. Compared to existing works, experimental results show reduction by 41.6% in latency and improvement by 16.9% in throughput with negligible extra energy consumption. Additional benefits in the network resource utilization and the performance under increasing network sizes are also analyzed.