Addressing the system-on-a-chip interconnect woes through communication-based design
Proceedings of the 38th annual Design Automation Conference
Application-Specific System-on-a-Chip Multiprocessors
IEEE Design & Test
Networks on Chip: A New Paradigm for Systems on Chip Design
Proceedings of the conference on Design, automation and test in Europe
On-chip networks: A scalable, communication-centric embedded system design paradigm
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
IEEE Transactions on Computers
Automatic network generation for system-on-chip communication design
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
Overview of the MPSoC design challenge
Proceedings of the 43rd annual Design Automation Conference
Design tradeoffs for tiled CMP on-chip networks
Proceedings of the 20th annual international conference on Supercomputing
Leveraging Optical Technology in Future Bus-based Chip Multiprocessors
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Corona: System Implications of Emerging Nanophotonic Technology
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors
IEEE Transactions on Computers
Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics
HOTI '08 Proceedings of the 2008 16th IEEE Symposium on High Performance Interconnects
Firefly: illuminating future network-on-chip with nanophotonics
Proceedings of the 36th annual international symposium on Computer architecture
A Low-power Low-cost Optical Router for Optical Networks-on-Chip in Multiprocessor Systems-on-Chip
ISVLSI '09 Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI
A Hierarchical Hybrid Optical-Electronic Network-on-Chip
ISVLSI '10 Proceedings of the 2010 IEEE Annual Symposium on VLSI
Enabling quality-of-service in nanophotonic network-on-chip
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip
ISVLSI '11 Proceedings of the 2011 IEEE Computer Society Annual Symposium on VLSI
| Hi-index | 0.00 |
The efficiency of collaboration among processors is a critical design metric for multiprocessor systems-on-chip (MPSoCs). It is the communication architecture that determines the collaboration efficiency on the hardware side. Optical NoCs, which are based on optical interconnects and optical routers, offer a new approach to empowering ultra-high bandwidth with low power consumption. In this paper, we provide a detailed study on the floorplans of optical NoCs in two popular two-dimensional topologies: mesh and torus. The study covers important design metrics for mesh and torus-based optical NoCs, such as the number of waveguide crossings in the floorplan and the number of paths and hops. We summarize the results into equations, taking all the dimensional cases into consideration. Based on this study, as well as the properties of the XY routing algorithm, we propose several approaches to optimize the power efficiency of optical NoCs by minimizing the number of waveguide crossings in the floorplan. We show the optimization procedures for torus-based optical NoCs in all possible cases. Comparison results show that the floorplan optimization reduces waveguide crossings significantly within the entire network as well as in longest paths. As is suggested in this paper, the number of waveguide crossings represents power loss in the optical NoC. By minimizing the number of waveguide crossings in the optimized floorplans, the energy efficiency of the optical NoC is improved than the original designs.