System-level modeling and analysis of thermal effects in optical networks-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Microprocessors & Microsystems
| Hi-index | 0.00 |
The performance of multiprocessor systems, such as chip multiprocessors (CMPs), is determined not only by the performance of their processors, but also by how efficiently they collaborate with one another. It is the communication architectures which determine the collaboration efficiency on the hardware side. Optical networks-on-chip (ONoCs) are emerging communication architectures that can potentially offer ultra-high communication bandwidth and low latency to multiprocessor systems. Thermal sensitivity is an intrinsic characteristic of photonic devices used by ONoCs as well as a potential issue. For the first time, this paper systematically modeled and quantitatively analyzed the thermal effects in ONoCs and their impacts. We presented an analytical ONoC thermal model, and show that on-chip temperature fluctuations can dramatically reduce the worst-case ONoC power efficiency. For instance, the power efficiency of an ONoC will drop to about 5pJ/bit when chip temperature reaches 85oC. We revealed three important factors regarding ONoC power efficiency under temperature variations, and found the optimal initial device conditions to minimize thermal impacts. The impacts of the thermal effects on the ONoC power consumption under different chip temperatures, device characteristics, and ONoC configurations are quantitatively analyzed. The findings in this paper can help support the further development of this emerging technology.