On-Chip photonic interconnects for scalable multi-core architectures

Authors:
Avinash Karanth Kodi;Randy Morris;Ahmed Louri;Xiang Zhang
Affiliations:
School of Electrical Engineering and Computer Science, Ohio University, Athens, 45701, USA;School of Electrical Engineering and Computer Science, Ohio University, Athens, 45701, USA;Electrical and Computer Engineering, University of Arizona, Tucson, 85721, USA;Electrical and Computer Engineering, University of Arizona, Tucson, 85721, USA
Venue:
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Year:
2009

Citing 1
Cited 1

Research Challenges for On-Chip Interconnection Networks

IEEE Micro

System-level modeling and analysis of thermal effects in optical networks-on-chip

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper, we propose PROPEL, a photonic network-on-chip (NoC) that improves performance and power with energy-efficient opto-electronic components for future chip multiprocessors (CMPs). Our analytical and simulation results indicate that PROPEL improves throughput and reduces power over optical and electrical networks for various traffic traces while requiring fewer photonic components and devices.