3D CMOS SOL for high performance computing
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Carbon nanotubes in interconnect applications
Microelectronic Engineering
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
Interconnect-power dissipation in a microprocessor
Proceedings of the 2004 international workshop on System level interconnect prediction
Predictions of CMOS compatible on-chip optical interconnect
Proceedings of the 2005 international workshop on System level interconnect prediction
Demystifying 3D ICs: The Pros and Cons of Going Vertical
IEEE Design & Test
Placement and Routing in 3D Integrated Circuits
IEEE Design & Test
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Performance analysis of carbon nanotube interconnects for VLSI applications
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Are carbon nanotubes the future of VLSI interconnections?
Proceedings of the 43rd annual Design Automation Conference
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Proceedings of the 2007 international symposium on Physical design
IEEE Transactions on Nanotechnology
Return-limited inductances: a practical approach to on-chip inductance extraction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.00 |
This paper looks at the CAD implications of possible new interconnect technologies. We consider three technologies in particular: three dimensional ICs, carbon nanotubes as a replacement for metal interconnects, and optical interconnections for longer range on-chip communication. Each of these requires new CAD support to be used effectively.