A survey of power estimation techniques in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
LP/LV circuits: state of the art and prospects
Proceedings of the first session on Low-power, low-voltage integrated circuits : technology and design: technology and design
Modeling power consumption in arithmetic operators
Proceedings of the first session on Low-power, low-voltage integrated circuits : technology and design: technology and design
Low Power Digital CMOS Design
Vertically integrated SOI circuits for low-power and high-performance applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Overlay as the key to drive wafer scale 3D integration
Microelectronic Engineering
CAD implications of new interconnect technologies
Proceedings of the 44th annual Design Automation Conference
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This paper addresses three topics: First, a new three-dimensional CMOS-SOI on SOI technology is presented, then design methodologies are proposed for this technology and last, a comparison is carried out between 2D and 3D designs. In this technology the P-channel devices are stacked over the N-channel ones. All gates are l00nm length. New design constraints are introduced. Consequently, new design methodologies have to be developed in order to fully take advantage of the outstanding features of 3D integration like for example the reduced length of interconnections. A 16×l6 bit multiplier was designed in this technology. Comparative results between 2D and 3D integration are given here in terms of energy consumption, delay and area