Interconnect analysis: from 3-D structures to circuit models
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A quick safari through the reconfiguration jungle
Proceedings of the 38th annual Design Automation Conference
Inductance 101: modeling and extraction
Proceedings of the 38th annual Design Automation Conference
Inductance 101: analysis and design issues
Proceedings of the 38th annual Design Automation Conference
An interconnect energy model considering coupling effects
Proceedings of the 38th annual Design Automation Conference
Uncertainty-aware circuit optimization
Proceedings of the 39th annual Design Automation Conference
Time-Domain Simulation of Variational Interconnect Models
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
Three-Dimensional Integrated Circuits: Performance, Design Methodology, and CAD Tools
ISVLSI '03 Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)
Statistical analysis of subthreshold leakage current for VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Variational delay metrics for interconnect timing analysis
Proceedings of the 41st annual Design Automation Conference
Global interconnect design in a three-dimensional system-on-a-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Accurate modeling of substrate resistive coupling for floating substrates
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Performance analysis of carbon nanotube interconnects for VLSI applications
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Power characteristics of inductive interconnect
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Luttinger liquid theory as a model of the gigahertz electrical properties of carbon nanotubes
IEEE Transactions on Nanotechnology
An RF circuit model for carbon nanotubes
IEEE Transactions on Nanotechnology
Managing on-chip inductive effects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Interconnect sizing and spacing with consideration of coupling capacitance
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast on-chip inductance simulation using a precorrected-FFT method
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
BALBOA: a component-based design environment for system models
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Assessing carbon nanotube bundle interconnect for future FPGA architectures
Proceedings of the conference on Design, automation and test in Europe
CAD implications of new interconnect technologies
Proceedings of the 44th annual Design Automation Conference
Engineering of Software-Intensive Systems: State of the Art and Research Challenges
Software-Intensive Systems and New Computing Paradigms
FPCNA: a field programmable carbon nanotube array
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
On the modeling of resistance in graphene nanoribbon (GNR) for future interconnect applications
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Closed-form solution for timing analysis of process variations on SWCNT interconnect
Proceedings of the 11th international workshop on System level interconnect prediction
Design and evaluation of a carbon nanotube-based programmable architecture
International Journal of Parallel Programming
Emerging carbon nanotube electronic circuits, modeling, and performance
VLSI Design - Special issue on selected papers from the midwest symposium on circuits and systems
Reconfigurable circuit design with nanomaterials
Proceedings of the Conference on Design, Automation and Test in Europe
Journal of Computational Electronics
Journal of Computational Electronics
| Hi-index | 0.00 |
Single-walled carbon nanotube (SWCNT) bundles have the potential to provide an attractive solution for the resistivity and electromigration problems faced by traditional copper interconnect as technology scales into the nanoscale regime. In this article, we evaluate the performance and reliability of nanotube bundles for both local and global interconnect in future VLSI applications. To provide a holistic evaluation of SWCNT bundles for on-chip interconnect, we have developed an efficient equivalent circuit model that captures the statistical distribution of individual metallic and semiconducting nanotubes while accurately incorporating recent experimental and theoretical results on inductance, contact resistance, and ohmic resistance. Leveraging the circuit model, we examine the performance and reliability of nanotube bundles for both individual signal lines and system-level designs. SWCNT interconnect bundles can provide significant improvement in delay and maximum current density over traditional copper interconnect, depending on bundle geometry and process technology. However, for system-level designs, the statistical variation in the delay of SWCNT bundles may lead to reliability issues in future process technology. Consequently, if the SWCNT chirality can be effectively controlled and other manufacturing challenges are met, SWCNT bundles potentially are a viable alternative to standard copper interconnect as process technology scales.