Performance analysis of carbon nanotube interconnects for VLSI applications

Authors:
N. Srivastava;K. Banerjee
Affiliations:
Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA;Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
Venue:
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Year:
2005

Citing 5
Cited 28

Carbon nanotubes in interconnect applications

Microelectronic Engineering
A circuit model for carbon nanotube interconnects: comparative study with Cu interconnects for scaled technologies

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Single-walled carbon nanotube electronics

IEEE Transactions on Nanotechnology
Luttinger liquid theory as a model of the gigahertz electrical properties of carbon nanotubes

IEEE Transactions on Nanotechnology
Analysis of on-chip inductance effects for distributed RLC interconnects

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Electrothermal engineering in the nanometer era: from devices and interconnects to circuits and systems

ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Are carbon nanotubes the future of VLSI interconnections?

Proceedings of the 43rd annual Design Automation Conference
Modeling and design challenges and solutions for carbon nanotube-based interconnect in future high performance integrated circuits

ACM Journal on Emerging Technologies in Computing Systems (JETC)
On-Chip Communication Architectures: System on Chip Interconnect

On-Chip Communication Architectures: System on Chip Interconnect
Modeling of the performance of carbon nanotube bundle, cu/low-k and optical on-chip global interconnects

Proceedings of the 2007 international workshop on System level interconnect prediction
CAD implications of new interconnect technologies

Proceedings of the 44th annual Design Automation Conference
Low power FPGA design using hybrid CMOS-NEMS approach

ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Scaling and evaluation of carbon nanotube interconnects for VLSI applications

Proceedings of the 2nd international conference on Nano-Networks
FPCNA: a field programmable carbon nanotube array

Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Hybrid nanoelectronics: future of computer technology

Journal of Computer Science and Technology
OIL: a nano-photonics optical interconnect library for a new photonic networks-on-chip architecture

Proceedings of the 11th international workshop on System level interconnect prediction
Closed-form solution for timing analysis of process variations on SWCNT interconnect

Proceedings of the 11th international workshop on System level interconnect prediction
Design and evaluation of a carbon nanotube-based programmable architecture

International Journal of Parallel Programming
Intel LVS logic as a combinational logic paradigm in CNT technology

Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures
Neural network modeling of voltage-dependent resistance of metallic carbon nanotube interconnects: An ab initio study

Expert Systems with Applications: An International Journal
Reconfigurable circuit design with nanomaterials

Proceedings of the Conference on Design, Automation and Test in Europe
Using carbon nanotube in digital memories

NANOARCH '09 Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures
Evaluating carbon nanotube global interconnects for chip multiprocessor applications

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Resistive analysis of mixed carbon nanotube bundle interconnect and its comparison with copper interconnect

Proceedings of the International Conference & Workshop on Emerging Trends in Technology
Inductance modelling of SWCNT bundle interconnects using partial element equivalent circuit method

Journal of Computational Electronics
A physical design tool for carbon nanotube field-effect transistor circuits

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Modeling of single-wall carbon nanotube interconnects for different process, temperature, and voltage conditions and investigating timing delay

Journal of Computational Electronics
Carbon NanoTubes as suitable platform to signals recording of cardiac cells interfaced to metal microelectrodes: a modeling approach

Journal of Computational Electronics
Demystifying SWCNT-bundle-interconnects inductive behavior through novel modeling

Journal of Computational Electronics
Interconnect optimization to enhance the performance of subthreshold circuits

Microelectronics Journal
Traffic steering between a low-latency unswitched TL ring and a high-throughput switched on-chip interconnect

PACT '13 Proceedings of the 22nd international conference on Parallel architectures and compilation techniques
METEOR: Hybrid photonic ring-mesh network-on-chip for multicore architectures

ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers
Influence of distance between adjacent tubes on SWCNT bundle interconnect delay and power dissipation

Journal of Computational Electronics

Quantified Score

Hi-index	0.00

Visualization

Abstract

The work in this paper analyses the applicability of carbon nanotube (CNT) bundles as interconnects for VLSI circuits, while taking into account the practical limitations in this technology. A model is developed to calculate equivalent circuit parameters for a CNT-bundle interconnect based on interconnect geometry. Using this model, the performance of CNT-bundle interconnects (at local, intermediate and global levels) is compared to copper wires of the future. It is shown that CNT bundles can outperform copper for long intermediate and global interconnects, and can be engineered to compete with copper for local level interconnects. The technological requirements necessary to make CNT bundles viable as future interconnects are also laid out.