Inductance modelling of SWCNT bundle interconnects using partial element equivalent circuit method

Authors:
Sudhanshu Choudhary;S. Qureshi
Affiliations:
VLSI/EDA Lab, Department of Electrical Engineering, Indian Institute of Technology, Kanpur, India;VLSI/EDA Lab, Department of Electrical Engineering, Indian Institute of Technology, Kanpur, India
Venue:
Journal of Computational Electronics
Year:
2011

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Abstract

Partial element equivalent circuit method (PEEC) is used to model the total loop inductance of a single wall carbon nanotube (SWCNT) bundle interconnects in a ground-signal-ground (GSG) configuration. Nanotube bundle is modelled as an equivalent rectangular conductor using the proposed equivalent area model, where the conductor area is determined by the area of single nanotube and total number of nanotubes in the bundle. Magnetic inductance and total inductance are calculated after obtaining the partial mutual and partial self inductance values from this method. The effects of spacing to width ratio and wire length over the total inductance are also presented in this paper.