Molecular electronics: devices, systems and tools for gigagate, gigabit chips
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
ALLCN: An Automatic Logic-to-Layout Tool for Carbon Nanotube Based Nanotechnology
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Performance analysis of carbon nanotube interconnects for VLSI applications
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architecture
Proceedings of the 43rd annual Design Automation Conference
Proceedings of the 44th annual Design Automation Conference
Automated design of misaligned-carbon-nanotube-immune circuits
Proceedings of the 44th annual Design Automation Conference
Carbon nanotube transistor compact model for circuit design and performance optimization
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Design guidelines for metallic-carbon-nanotube-tolerant digital logic circuits
Proceedings of the conference on Design, automation and test in Europe
Carbon nanotube circuits in the presence of carbon nanotube density variations
Proceedings of the 46th Annual Design Automation Conference
Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesis
Proceedings of the Conference on Design, Automation and Test in Europe
An RF circuit model for carbon nanotubes
IEEE Transactions on Nanotechnology
Threshold Voltage and On–Off Ratio Tuning for Multiple-Tube Carbon Nanotube FETs
IEEE Transactions on Nanotechnology
A circuit-compatible model of ballistic carbon nanotube field-effect transistors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this article, we present a graphical Computer-Aided Design (CAD) environment for the design, analysis, and layout of Carbon NanoTube (CNT) Field-Effect Transistor (CNFET) circuits. This work is motivated by the fact that such a tool currently does not exist in the public domain for researchers. Our tool has been integrated within Electric a very powerful, yet free CAD system for custom design of Integrated Circuits (ICs). The tool supports CNFET schematic and layout entry, rule checking, and HSpice/VerilogA netlist generation. We provide users with a customizable CNFET technology library with the ability to specify λ-based design rules. We showcase the capabilities of our tool by demonstrating the design of a large CNFET standard cell and components library. Meanwhile, HSPICE simulations also have been presented for cell library characterization. We hope that the availability of this tool will invigorate the CAD community to explore novel ideas in CNFET circuit design.