ALLCN: An Automatic Logic-to-Layout Tool for Carbon Nanotube Based Nanotechnology
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Modeling and analysis of circuit performance of ballistic CNFET
Proceedings of the 43rd annual Design Automation Conference
Compact modeling of carbon nanotube transistor for early stage process-design exploration
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Proceedings of the 20th annual conference on Integrated circuits and systems design
Prospect of ballistic CNFET in high performance applications: Modeling and analysis
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Carbon nanotube transistor compact model for circuit design and performance optimization
ACM Journal on Emerging Technologies in Computing Systems (JETC)
A circuit-compatible analytical device model for ballistic nanowire transistors
Microelectronics Journal
Proceedings of the conference on Design, automation and test in Europe
FPCNA: a field programmable carbon nanotube array
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Graphene nanoribbon FETs: technology exploration and CAD
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Performance comparison of CNFET- and CMOS-based 6T SRAM cell in deep submicron
Microelectronics Journal
The Predictive Technology Model in the Late Silicon Era and Beyond
Foundations and Trends in Electronic Design Automation
Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesis
Proceedings of the Conference on Design, Automation and Test in Europe
Analysis of CNT bundle and its comparison with copper interconnect for CMOS and CNFET drivers
Journal of Nanomaterials
A physical design tool for carbon nanotube field-effect transistor circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Improving the RF performance of carbon nanotube field effect transistor
Journal of Nanomaterials - Special issue on Low-Dimensional Carbon Nanomaterials 2012
Journal of Computational Electronics
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Carbon nanotube field-effect transistors (CNFETs) are being extensively studied as possible successors to CMOS. Novel device structures have been fabricated and device simulators have been developed to estimate their performance in a sub-10-nm transistor era. This paper presents a novel method of circuit-compatible modeling of single-walled semiconducting CNFETs in their ultimate performance limit. For the first time, both the I-V and the C-V characteristics of the device have been efficiently modeled for circuit simulations. The model so developed has been used to simulate arithmetic and logic blocks using HSPICE.