Modeling and analysis of circuit performance of ballistic CNFET
Proceedings of the 43rd annual Design Automation Conference
Carbon nanotube transistor circuits: models and tools for design and performance optimization
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A circuit-compatible model of ballistic carbon nanotube field-effect transistors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Carbon nanotube transistor compact model for circuit design and performance optimization
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Graphene nanoribbon FETs: technology exploration and CAD
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Digital VLSI logic technology using Carbon Nanotube FETs: frequently asked questions
Proceedings of the 46th Annual Design Automation Conference
The Predictive Technology Model in the Late Silicon Era and Beyond
Foundations and Trends in Electronic Design Automation
Semi-analytical model for schottky-barrier carbon nanotube and graphene nanoribbon transistors
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Analytical modeling of high performance single-walled carbon nanotube field-effect-transistor
Microelectronics Journal
What is Predictive Technology Model (PTM)?
ACM SIGDA Newsletter
Impact of RDF and RTS on the performance of SRAM cells
Journal of Computational Electronics
Construction of SEU tolerant flip-flops allowing enhanced scan delay fault testing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Universal logic modules based on double-gate carbon nanotube transistors
Proceedings of the 48th Design Automation Conference
Carbon nanotube imperfection-immune digital VLSI: frequently asked questions updated
Proceedings of the International Conference on Computer-Aided Design
Timing-Error-Detecting Dual-Edge-Triggered Flip-Flop
Journal of Electronic Testing: Theory and Applications
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Carbon nanotube transistor (CNT) is promising to be the technology of choice for nanoscale integration. In this work, we develop the first compact model of CNT, with the objective to explore the optimal process and design space for robust low-power applications. Based on the concept of the surface potential, the new model accurately predicts the characteristics of a CNT device under various process and design conditions, such as diameter, chirality, gate dielectrics, and bias voltages. With the physical modeling of the contact, this model covers both the Schottky-barrier CNT (SB-CNT) and MOS-type CNT. The proposed model does not require any iteration and thus, significantly enhances the simulation efficiency to support large-scale design research. Using this model, we benchmark the performance of a FO4 inverter with CNT and 22nm CMOS technology. The following key insights are extracted: (1) even with the SB-CNT and realistic layout parasitics, the circuit speed can be more than 10X that of 22nm CMOS; (2) The diameter range of 1-1.5nm exhibits the maximum tolerance to contact materials and process variations; (3) a CNT circuit allows better scaling of the supply voltage (Vdd) for power reduction. For a fixed energy consumption and Vdd, the CNT speed is 4X that of 22nm CMOS. Overall, the new model enables efficient design research with CNT, revealing tremendous opportunities for both high-speed and low-power applications.