Carbon nanotube transistor circuits: models and tools for design and performance optimization

Authors:
H.-S. Philip Wong;Jie Deng;Arash Hazeghi;Tejas Krishnamohan;Gordon C. Wan
Affiliations:
Stanford University, Stanford, CA;Stanford University, Stanford, CA;Stanford University, Stanford, CA;Stanford University, Stanford, CA;Stanford University, Stanford, CA
Venue:
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Year:
2006

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Abstract

In this paper, we describe the development of device models and tools for the design of new transistors such as the carbon nanotube transistor. An HSPICE model for enhancement mode nanotube transistor has been developed. It can be used for design of nanotube transistor circuits as well as to study performance benefits of the new transistor. A model of the carbon nanotube transistor with Schottky barrier is presented. The model enables device design and performance optimization.