Performance optimization of CNFET for ultra-low power reconfigurable architecture

Authors:
S. D. Pable;Mohd. Hasan
Affiliations:
Aligarh Muslim University, Aligarh, India;Aligarh Muslim University, Aligarh, India
Venue:
Proceedings of the 2011 International Conference on Communication, Computing & Security
Year:
2011

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Abstract

The designers of field programmable gate array (FPGAs) always devote to optimize the chip performance. The fabrication cost of ASICs is rising exponentially in deep submicron and hence it is important to investigate ways of reducing FPGA power consumption so that they can also deploy in place of ASICs in portable energy constrained applications. Minimum energy delay point occurs in subthreshold region and subthreshold operation of circuits shows order of power saving over superthreshold circuits. Therefore, it is also important to investigate the possibility of extending the use of FPGA even in subthreshold region for ultra low power applications. This paper investigates the subthreshold performance of a basic FPGA building block-a Look up Table (LUT). It presents the performance optimization of CNFET based fully encoded three inputs LUT in deep submicron (DSM) region for delay, power dissipation and switching energy. Proposed multi-chirality LUT implementation shows significant advantages in delay as well as switching energy.