Digital VLSI logic technology using Carbon Nanotube FETs: frequently asked questions
Proceedings of the 46th Annual Design Automation Conference
Probabilistic analysis and design of metallic-carbon-nanotube-tolerant digital logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Performance assessment of analog circuits with carbon nanotube FET (CNFET)
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Design methodology for Carbon Nanotube based circuits in the presence of metallic tubes
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures
Intel LVS logic as a combinational logic paradigm in CNT technology
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures
Carbon nanotube circuits: living with imperfections and variations
Proceedings of the Conference on Design, Automation and Test in Europe
Imperfection-immune VLSI logic circuits using carbon nanotube field effect transistors
Proceedings of the Conference on Design, Automation and Test in Europe
Performance optimization of CNFET for ultra-low power reconfigurable architecture
Proceedings of the 2011 International Conference on Communication, Computing & Security
Influence of metallic tubes on the reliability of CNTFET SRAMs: error mechanisms and countermeasures
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Universal logic modules based on double-gate carbon nanotube transistors
Proceedings of the 48th Design Automation Conference
Robustness comparison of emerging devices for portable applications
Journal of Nanomaterials
Design and Analysis of a Robust Carbon Nanotube-Based Asynchronous Primitive Circuit
ACM Journal on Emerging Technologies in Computing Systems (JETC)
On the Delay of a CNTFET with Undeposited CNTs by Gate Width Adjustment
Journal of Electronic Testing: Theory and Applications
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Carbon nanotubes (CNTs) show great promise as extensions to silicon CMOS due to their excellent electronic properties and extremely small size. Using a Carbon Nanotube Field Effect Transistor (CNFET) SPICE model, we evaluate circuit-level performance of CNFET technology in the presence of CNT fabrication-related nonidealities and imperfections, and parasitic resistances and capacitances extracted from the CNFET circuit layout. We use Monte Carlo simulations using the CNFET SPICE model to investigate the effects of three major CNT process-related imperfections on circuit-level performance: 1) doping variations in the CNFET source and drain regions; 2) CNT diameter variations; and 3) variations caused by the removal of metallic CNTs. The simulation results indicate that metallic CNT removal has the most impact on CNFET variation; less than 8% of CNTs grown should be metallic to reduce circuit performance variation. This paper also presents an analytical model for the scalability of CNFET technology. High CNT density (250 CNTs/mum) is critical to ensure that performance (delay and energy) gains over silicon CMOS are maintained or improved with shrinking lithographic dimensions.