Design methodology for Carbon Nanotube based circuits in the presence of metallic tubes

Authors:
Rehman Ashraf;Rajeev K. Nain;Malgorzata Chrzanowska-Jeske;Siva G. Narendra
Affiliations:
Portland State University, Portland, OR;Portland State University, Portland, OR;Portland State University, Portland, OR;Portland State University, Portland, OR
Venue:
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures
Year:
2010

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Abstract

Carbon Nanotube Field Effect Transistor (CNFET) has a potential to become successor of Si-CMOS devices because of its excellent electronic properties. One of the most important challenges for the CNT-based technology is the undesired presence of metallic tubes which adversely impacts the performance, power and yield of CNT based circuits. Different tube configurations in CNFET transistor like Parallel Tube (PT) and Transistor Stacking (TrS) can be used to trade-off yield for performance. The Monte Carlo (MC) simulations of a full adder show that TrS implementation along with parallelism in the critical path can result in the same performance as the PT implementation (demonstrated significant improvements over CMOS) but with 4X increased functional yield and 6X reduced static power. Furthermore, we proposed architecture based on regular logic bricks that are designed using different tube configurations. Monte Carlo simulations show that for 10% metallic tubes logic bricks implemented with hybrid configurations of CNFETs can help to reduce the performance impact by 2X as compared to homogeneous bricks implemented with only TrS CNFETs. In comparison to homogeneous bricks realized with only PT CNFETs, the static power can be reduced by 2X and yield can be increased from 22% to 54%.