Probabilistic analysis and design of metallic-carbon-nanotube-tolerant digital logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design methodology for Carbon Nanotube based circuits in the presence of metallic tubes
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures
IEEE Transactions on Nanotechnology
Wafer-Scale Growth and Transfer of Aligned Single-Walled Carbon Nanotubes
IEEE Transactions on Nanotechnology
Design Methods for Misaligned and Mispositioned Carbon-Nanotube Immune Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper deals with the performance of a Carbon Nano Tube Field Effect Transistor (CNTFET) in the presence of undeposited CNTs as defects. A simulation-based analysis of delay degradation due to different features (such as chirality and defective CNT distribution) is initially pursued. Two solutions to mitigate the change in delay are proposed; these approaches are based on adjusting the gate width of the CNTFET by lithography (and removing CNTs) as part of the fabrication process. These two methods reduce the average delay and its deviation, respectively. A probabilistic delay analysis is then presented. The performance of the proposed two adjustment methods is evaluated by considering CNT features (such as chirality and defect distribution) deterministically and probabilistically. By deterministic (probabilistic) simulation, the first method reduces on average the delay by 6.968 % (7.811 %) while the deviation is increased (decreased) by 32.444 % (9.788 %). The second method reduces deterministically (probabilistically) on average the deviation by 44.159 % (47.476 %) with 2.166 % (4.409 %) delay reduction.